
event-utc:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004005d8 <_init>:
  4005d8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4005dc:	910003fd 	mov	x29, sp
  4005e0:	9400003e 	bl	4006d8 <call_weak_fn>
  4005e4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4005e8:	d65f03c0 	ret

Disassembly of section .plt:

00000000004005f0 <.plt>:
  4005f0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4005f4:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf468>
  4005f8:	f947fe11 	ldr	x17, [x16, #4088]
  4005fc:	913fe210 	add	x16, x16, #0xff8
  400600:	d61f0220 	br	x17
  400604:	d503201f 	nop
  400608:	d503201f 	nop
  40060c:	d503201f 	nop

0000000000400610 <sprintf@plt>:
  400610:	b0000090 	adrp	x16, 411000 <sprintf@GLIBC_2.17>
  400614:	f9400211 	ldr	x17, [x16]
  400618:	91000210 	add	x16, x16, #0x0
  40061c:	d61f0220 	br	x17

0000000000400620 <clock_gettime@plt>:
  400620:	b0000090 	adrp	x16, 411000 <sprintf@GLIBC_2.17>
  400624:	f9400611 	ldr	x17, [x16, #8]
  400628:	91002210 	add	x16, x16, #0x8
  40062c:	d61f0220 	br	x17

0000000000400630 <__libc_start_main@plt>:
  400630:	b0000090 	adrp	x16, 411000 <sprintf@GLIBC_2.17>
  400634:	f9400a11 	ldr	x17, [x16, #16]
  400638:	91004210 	add	x16, x16, #0x10
  40063c:	d61f0220 	br	x17

0000000000400640 <gettimeofday@plt>:
  400640:	b0000090 	adrp	x16, 411000 <sprintf@GLIBC_2.17>
  400644:	f9400e11 	ldr	x17, [x16, #24]
  400648:	91006210 	add	x16, x16, #0x18
  40064c:	d61f0220 	br	x17

0000000000400650 <gmtime@plt>:
  400650:	b0000090 	adrp	x16, 411000 <sprintf@GLIBC_2.17>
  400654:	f9401211 	ldr	x17, [x16, #32]
  400658:	91008210 	add	x16, x16, #0x20
  40065c:	d61f0220 	br	x17

0000000000400660 <__gmon_start__@plt>:
  400660:	b0000090 	adrp	x16, 411000 <sprintf@GLIBC_2.17>
  400664:	f9401611 	ldr	x17, [x16, #40]
  400668:	9100a210 	add	x16, x16, #0x28
  40066c:	d61f0220 	br	x17

0000000000400670 <abort@plt>:
  400670:	b0000090 	adrp	x16, 411000 <sprintf@GLIBC_2.17>
  400674:	f9401a11 	ldr	x17, [x16, #48]
  400678:	9100c210 	add	x16, x16, #0x30
  40067c:	d61f0220 	br	x17

0000000000400680 <printf@plt>:
  400680:	b0000090 	adrp	x16, 411000 <sprintf@GLIBC_2.17>
  400684:	f9401e11 	ldr	x17, [x16, #56]
  400688:	9100e210 	add	x16, x16, #0x38
  40068c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400690 <_start>:
  400690:	d280001d 	mov	x29, #0x0                   	// #0
  400694:	d280001e 	mov	x30, #0x0                   	// #0
  400698:	aa0003e5 	mov	x5, x0
  40069c:	f94003e1 	ldr	x1, [sp]
  4006a0:	910023e2 	add	x2, sp, #0x8
  4006a4:	910003e6 	mov	x6, sp
  4006a8:	580000c0 	ldr	x0, 4006c0 <_start+0x30>
  4006ac:	580000e3 	ldr	x3, 4006c8 <_start+0x38>
  4006b0:	58000104 	ldr	x4, 4006d0 <_start+0x40>
  4006b4:	97ffffdf 	bl	400630 <__libc_start_main@plt>
  4006b8:	97ffffee 	bl	400670 <abort@plt>
  4006bc:	00000000 	.inst	0x00000000 ; undefined
  4006c0:	0040097c 	.word	0x0040097c
  4006c4:	00000000 	.word	0x00000000
  4006c8:	00400a88 	.word	0x00400a88
  4006cc:	00000000 	.word	0x00000000
  4006d0:	00400b08 	.word	0x00400b08
  4006d4:	00000000 	.word	0x00000000

00000000004006d8 <call_weak_fn>:
  4006d8:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf468>
  4006dc:	f947f000 	ldr	x0, [x0, #4064]
  4006e0:	b4000040 	cbz	x0, 4006e8 <call_weak_fn+0x10>
  4006e4:	17ffffdf 	b	400660 <__gmon_start__@plt>
  4006e8:	d65f03c0 	ret
  4006ec:	00000000 	.inst	0x00000000 ; undefined

00000000004006f0 <deregister_tm_clones>:
  4006f0:	b0000080 	adrp	x0, 411000 <sprintf@GLIBC_2.17>
  4006f4:	91014000 	add	x0, x0, #0x50
  4006f8:	b0000081 	adrp	x1, 411000 <sprintf@GLIBC_2.17>
  4006fc:	91014021 	add	x1, x1, #0x50
  400700:	eb00003f 	cmp	x1, x0
  400704:	540000a0 	b.eq	400718 <deregister_tm_clones+0x28>  // b.none
  400708:	90000001 	adrp	x1, 400000 <_init-0x5d8>
  40070c:	f9459421 	ldr	x1, [x1, #2856]
  400710:	b4000041 	cbz	x1, 400718 <deregister_tm_clones+0x28>
  400714:	d61f0020 	br	x1
  400718:	d65f03c0 	ret
  40071c:	d503201f 	nop

0000000000400720 <register_tm_clones>:
  400720:	b0000080 	adrp	x0, 411000 <sprintf@GLIBC_2.17>
  400724:	91014000 	add	x0, x0, #0x50
  400728:	b0000081 	adrp	x1, 411000 <sprintf@GLIBC_2.17>
  40072c:	91014021 	add	x1, x1, #0x50
  400730:	cb000021 	sub	x1, x1, x0
  400734:	9343fc21 	asr	x1, x1, #3
  400738:	8b41fc21 	add	x1, x1, x1, lsr #63
  40073c:	9341fc21 	asr	x1, x1, #1
  400740:	b40000a1 	cbz	x1, 400754 <register_tm_clones+0x34>
  400744:	90000002 	adrp	x2, 400000 <_init-0x5d8>
  400748:	f9459842 	ldr	x2, [x2, #2864]
  40074c:	b4000042 	cbz	x2, 400754 <register_tm_clones+0x34>
  400750:	d61f0040 	br	x2
  400754:	d65f03c0 	ret

0000000000400758 <__do_global_dtors_aux>:
  400758:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40075c:	910003fd 	mov	x29, sp
  400760:	f9000bf3 	str	x19, [sp, #16]
  400764:	b0000093 	adrp	x19, 411000 <sprintf@GLIBC_2.17>
  400768:	39416260 	ldrb	w0, [x19, #88]
  40076c:	35000080 	cbnz	w0, 40077c <__do_global_dtors_aux+0x24>
  400770:	97ffffe0 	bl	4006f0 <deregister_tm_clones>
  400774:	52800020 	mov	w0, #0x1                   	// #1
  400778:	39016260 	strb	w0, [x19, #88]
  40077c:	f9400bf3 	ldr	x19, [sp, #16]
  400780:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400784:	d65f03c0 	ret

0000000000400788 <frame_dummy>:
  400788:	17ffffe6 	b	400720 <register_tm_clones>

000000000040078c <convert_utc_time>:
  40078c:	d10103ff 	sub	sp, sp, #0x40
  400790:	a9017bfd 	stp	x29, x30, [sp, #16]
  400794:	910043fd 	add	x29, sp, #0x10
  400798:	f9000fa0 	str	x0, [x29, #24]
  40079c:	f9000ba1 	str	x1, [x29, #16]
  4007a0:	f90013bf 	str	xzr, [x29, #32]
  4007a4:	f9400fa0 	ldr	x0, [x29, #24]
  4007a8:	f100001f 	cmp	x0, #0x0
  4007ac:	54000101 	b.ne	4007cc <convert_utc_time+0x40>  // b.any
  4007b0:	f9400ba0 	ldr	x0, [x29, #16]
  4007b4:	90000001 	adrp	x1, 400000 <_init-0x5d8>
  4007b8:	912ce021 	add	x1, x1, #0xb38
  4007bc:	f9400021 	ldr	x1, [x1]
  4007c0:	f9000001 	str	x1, [x0]
  4007c4:	12800000 	mov	w0, #0xffffffff            	// #-1
  4007c8:	14000034 	b	400898 <convert_utc_time+0x10c>
  4007cc:	f9400fa0 	ldr	x0, [x29, #24]
  4007d0:	d343fc01 	lsr	x1, x0, #3
  4007d4:	d29ef9e0 	mov	x0, #0xf7cf                	// #63439
  4007d8:	f2bc6a60 	movk	x0, #0xe353, lsl #16
  4007dc:	f2d374a0 	movk	x0, #0x9ba5, lsl #32
  4007e0:	f2e41880 	movk	x0, #0x20c4, lsl #48
  4007e4:	9bc07c20 	umulh	x0, x1, x0
  4007e8:	d344fc01 	lsr	x1, x0, #4
  4007ec:	d28e1000 	mov	x0, #0x7080                	// #28800
  4007f0:	8b000020 	add	x0, x1, x0
  4007f4:	f90013a0 	str	x0, [x29, #32]
  4007f8:	910083a0 	add	x0, x29, #0x20
  4007fc:	97ffff95 	bl	400650 <gmtime@plt>
  400800:	f90017a0 	str	x0, [x29, #40]
  400804:	f94017a0 	ldr	x0, [x29, #40]
  400808:	b9401400 	ldr	w0, [x0, #20]
  40080c:	111db008 	add	w8, w0, #0x76c
  400810:	f94017a0 	ldr	x0, [x29, #40]
  400814:	b9401000 	ldr	w0, [x0, #16]
  400818:	11000403 	add	w3, w0, #0x1
  40081c:	f94017a0 	ldr	x0, [x29, #40]
  400820:	b9400c04 	ldr	w4, [x0, #12]
  400824:	f94017a0 	ldr	x0, [x29, #40]
  400828:	b9400805 	ldr	w5, [x0, #8]
  40082c:	f94017a0 	ldr	x0, [x29, #40]
  400830:	b9400406 	ldr	w6, [x0, #4]
  400834:	f94017a0 	ldr	x0, [x29, #40]
  400838:	b9400007 	ldr	w7, [x0]
  40083c:	f9400fa0 	ldr	x0, [x29, #24]
  400840:	2a0003e1 	mov	w1, w0
  400844:	5289ba60 	mov	w0, #0x4dd3                	// #19923
  400848:	72a20c40 	movk	w0, #0x1062, lsl #16
  40084c:	9b207c20 	smull	x0, w1, w0
  400850:	d360fc00 	lsr	x0, x0, #32
  400854:	13067c02 	asr	w2, w0, #6
  400858:	131f7c20 	asr	w0, w1, #31
  40085c:	4b000040 	sub	w0, w2, w0
  400860:	52807d02 	mov	w2, #0x3e8                 	// #1000
  400864:	1b027c00 	mul	w0, w0, w2
  400868:	4b000020 	sub	w0, w1, w0
  40086c:	90000001 	adrp	x1, 400000 <_init-0x5d8>
  400870:	912d0021 	add	x1, x1, #0xb40
  400874:	b90003e0 	str	w0, [sp]
  400878:	2a0803e2 	mov	w2, w8
  40087c:	f9400ba0 	ldr	x0, [x29, #16]
  400880:	97ffff64 	bl	400610 <sprintf@plt>
  400884:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  400888:	912da000 	add	x0, x0, #0xb68
  40088c:	f9400ba1 	ldr	x1, [x29, #16]
  400890:	97ffff7c 	bl	400680 <printf@plt>
  400894:	52800000 	mov	w0, #0x0                   	// #0
  400898:	a9417bfd 	ldp	x29, x30, [sp, #16]
  40089c:	910103ff 	add	sp, sp, #0x40
  4008a0:	d65f03c0 	ret

00000000004008a4 <XAG_TIME_COMMON_GetMonotonic>:
  4008a4:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4008a8:	910003fd 	mov	x29, sp
  4008ac:	910083a0 	add	x0, x29, #0x20
  4008b0:	aa0003e1 	mov	x1, x0
  4008b4:	52800000 	mov	w0, #0x0                   	// #0
  4008b8:	97ffff5a 	bl	400620 <clock_gettime@plt>
  4008bc:	f94013a1 	ldr	x1, [x29, #32]
  4008c0:	b0000080 	adrp	x0, 411000 <sprintf@GLIBC_2.17>
  4008c4:	91014000 	add	x0, x0, #0x50
  4008c8:	f9400000 	ldr	x0, [x0]
  4008cc:	cb000020 	sub	x0, x1, x0
  4008d0:	f9000ba0 	str	x0, [x29, #16]
  4008d4:	f94017a0 	ldr	x0, [x29, #40]
  4008d8:	d29ef9e1 	mov	x1, #0xf7cf                	// #63439
  4008dc:	f2bc6a61 	movk	x1, #0xe353, lsl #16
  4008e0:	f2d374a1 	movk	x1, #0x9ba5, lsl #32
  4008e4:	f2e41881 	movk	x1, #0x20c4, lsl #48
  4008e8:	9b417c01 	smulh	x1, x0, x1
  4008ec:	9347fc21 	asr	x1, x1, #7
  4008f0:	937ffc00 	asr	x0, x0, #63
  4008f4:	cb000020 	sub	x0, x1, x0
  4008f8:	f9000fa0 	str	x0, [x29, #24]
  4008fc:	a94107a0 	ldp	x0, x1, [x29, #16]
  400900:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400904:	d65f03c0 	ret

0000000000400908 <GetSystemClock>:
  400908:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  40090c:	910003fd 	mov	x29, sp
  400910:	910043a0 	add	x0, x29, #0x10
  400914:	d2800001 	mov	x1, #0x0                   	// #0
  400918:	97ffff4a 	bl	400640 <gettimeofday@plt>
  40091c:	f9400ba0 	ldr	x0, [x29, #16]
  400920:	f90017a0 	str	x0, [x29, #40]
  400924:	f94017a1 	ldr	x1, [x29, #40]
  400928:	aa0103e0 	mov	x0, x1
  40092c:	d37be800 	lsl	x0, x0, #5
  400930:	cb010000 	sub	x0, x0, x1
  400934:	d37ef400 	lsl	x0, x0, #2
  400938:	8b010000 	add	x0, x0, x1
  40093c:	d37df000 	lsl	x0, x0, #3
  400940:	aa0003e2 	mov	x2, x0
  400944:	f9400fa0 	ldr	x0, [x29, #24]
  400948:	d29ef9e1 	mov	x1, #0xf7cf                	// #63439
  40094c:	f2bc6a61 	movk	x1, #0xe353, lsl #16
  400950:	f2d374a1 	movk	x1, #0x9ba5, lsl #32
  400954:	f2e41881 	movk	x1, #0x20c4, lsl #48
  400958:	9b417c01 	smulh	x1, x0, x1
  40095c:	9347fc21 	asr	x1, x1, #7
  400960:	937ffc00 	asr	x0, x0, #63
  400964:	cb000020 	sub	x0, x1, x0
  400968:	8b000040 	add	x0, x2, x0
  40096c:	f90013a0 	str	x0, [x29, #32]
  400970:	f94013a0 	ldr	x0, [x29, #32]
  400974:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400978:	d65f03c0 	ret

000000000040097c <main>:
  40097c:	a9bb7bfd 	stp	x29, x30, [sp, #-80]!
  400980:	910003fd 	mov	x29, sp
  400984:	a902ffbf 	stp	xzr, xzr, [x29, #40]
  400988:	a903ffbf 	stp	xzr, xzr, [x29, #56]
  40098c:	f90027bf 	str	xzr, [x29, #72]
  400990:	97ffffc5 	bl	4008a4 <XAG_TIME_COMMON_GetMonotonic>
  400994:	a90187a0 	stp	x0, x1, [x29, #24]
  400998:	f9400fa1 	ldr	x1, [x29, #24]
  40099c:	aa0103e0 	mov	x0, x1
  4009a0:	d37be800 	lsl	x0, x0, #5
  4009a4:	cb010000 	sub	x0, x0, x1
  4009a8:	d37ef400 	lsl	x0, x0, #2
  4009ac:	8b010000 	add	x0, x0, x1
  4009b0:	d37df000 	lsl	x0, x0, #3
  4009b4:	aa0003e2 	mov	x2, x0
  4009b8:	f94013a0 	ldr	x0, [x29, #32]
  4009bc:	d29ef9e1 	mov	x1, #0xf7cf                	// #63439
  4009c0:	f2bc6a61 	movk	x1, #0xe353, lsl #16
  4009c4:	f2d374a1 	movk	x1, #0x9ba5, lsl #32
  4009c8:	f2e41881 	movk	x1, #0x20c4, lsl #48
  4009cc:	9b417c01 	smulh	x1, x0, x1
  4009d0:	9347fc21 	asr	x1, x1, #7
  4009d4:	937ffc00 	asr	x0, x0, #63
  4009d8:	cb000020 	sub	x0, x1, x0
  4009dc:	8b000040 	add	x0, x2, x0
  4009e0:	f90027a0 	str	x0, [x29, #72]
  4009e4:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  4009e8:	912e2000 	add	x0, x0, #0xb88
  4009ec:	f94027a1 	ldr	x1, [x29, #72]
  4009f0:	97ffff24 	bl	400680 <printf@plt>
  4009f4:	f90027bf 	str	xzr, [x29, #72]
  4009f8:	97ffffc4 	bl	400908 <GetSystemClock>
  4009fc:	f90027a0 	str	x0, [x29, #72]
  400a00:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  400a04:	912e2000 	add	x0, x0, #0xb88
  400a08:	f94027a1 	ldr	x1, [x29, #72]
  400a0c:	97ffff1d 	bl	400680 <printf@plt>
  400a10:	9100a3a0 	add	x0, x29, #0x28
  400a14:	aa0003e1 	mov	x1, x0
  400a18:	d2976880 	mov	x0, #0xbb44                	// #47940
  400a1c:	f2ac5540 	movk	x0, #0x62aa, lsl #16
  400a20:	97ffff5b 	bl	40078c <convert_utc_time>
  400a24:	9100a3a0 	add	x0, x29, #0x28
  400a28:	aa0003e1 	mov	x1, x0
  400a2c:	d28acb60 	mov	x0, #0x565b                	// #22107
  400a30:	f2ad95e0 	movk	x0, #0x6caf, lsl #16
  400a34:	97ffff56 	bl	40078c <convert_utc_time>
  400a38:	9100a3a0 	add	x0, x29, #0x28
  400a3c:	aa0003e1 	mov	x1, x0
  400a40:	d29e7460 	mov	x0, #0xf3a3                	// #62371
  400a44:	f2ae4b60 	movk	x0, #0x725b, lsl #16
  400a48:	97ffff51 	bl	40078c <convert_utc_time>
  400a4c:	9100a3a0 	add	x0, x29, #0x28
  400a50:	aa0003e1 	mov	x1, x0
  400a54:	d2836cc0 	mov	x0, #0x1b66                	// #7014
  400a58:	f2ae0880 	movk	x0, #0x7044, lsl #16
  400a5c:	f2c03020 	movk	x0, #0x181, lsl #32
  400a60:	97ffff4b 	bl	40078c <convert_utc_time>
  400a64:	9100a3a0 	add	x0, x29, #0x28
  400a68:	aa0003e1 	mov	x1, x0
  400a6c:	d29e9820 	mov	x0, #0xf4c1                	// #62657
  400a70:	f2ae0a20 	movk	x0, #0x7051, lsl #16
  400a74:	f2c03020 	movk	x0, #0x181, lsl #32
  400a78:	97ffff45 	bl	40078c <convert_utc_time>
  400a7c:	52800000 	mov	w0, #0x0                   	// #0
  400a80:	a8c57bfd 	ldp	x29, x30, [sp], #80
  400a84:	d65f03c0 	ret

0000000000400a88 <__libc_csu_init>:
  400a88:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400a8c:	910003fd 	mov	x29, sp
  400a90:	a901d7f4 	stp	x20, x21, [sp, #24]
  400a94:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf468>
  400a98:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf468>
  400a9c:	91374294 	add	x20, x20, #0xdd0
  400aa0:	913722b5 	add	x21, x21, #0xdc8
  400aa4:	a902dff6 	stp	x22, x23, [sp, #40]
  400aa8:	cb150294 	sub	x20, x20, x21
  400aac:	f9001ff8 	str	x24, [sp, #56]
  400ab0:	2a0003f6 	mov	w22, w0
  400ab4:	aa0103f7 	mov	x23, x1
  400ab8:	9343fe94 	asr	x20, x20, #3
  400abc:	aa0203f8 	mov	x24, x2
  400ac0:	97fffec6 	bl	4005d8 <_init>
  400ac4:	b4000194 	cbz	x20, 400af4 <__libc_csu_init+0x6c>
  400ac8:	f9000bb3 	str	x19, [x29, #16]
  400acc:	d2800013 	mov	x19, #0x0                   	// #0
  400ad0:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400ad4:	aa1803e2 	mov	x2, x24
  400ad8:	aa1703e1 	mov	x1, x23
  400adc:	2a1603e0 	mov	w0, w22
  400ae0:	91000673 	add	x19, x19, #0x1
  400ae4:	d63f0060 	blr	x3
  400ae8:	eb13029f 	cmp	x20, x19
  400aec:	54ffff21 	b.ne	400ad0 <__libc_csu_init+0x48>  // b.any
  400af0:	f9400bb3 	ldr	x19, [x29, #16]
  400af4:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400af8:	a942dff6 	ldp	x22, x23, [sp, #40]
  400afc:	f9401ff8 	ldr	x24, [sp, #56]
  400b00:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400b04:	d65f03c0 	ret

0000000000400b08 <__libc_csu_fini>:
  400b08:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400b0c <_fini>:
  400b0c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400b10:	910003fd 	mov	x29, sp
  400b14:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400b18:	d65f03c0 	ret
